1. Technical Field
The present disclosure relates to electrically erasable programmable read only memories (EEPROM). The present disclosure relates more particularly to an erasable and programmable memory, comprising memory cells each comprising a floating-gate transistor connected in series with a MOS-type access transistor.
2. Description of the Related Art
Such a memory cell functions based on the tunnel effect (or Fowler-Nordheim effect) which involves inducing displacements of the threshold voltage of the floating-gate transistor by injecting or withdrawing charges from the floating gate through a thin oxide layer separating the floating gate from a doped region. An operation of erasing or programming a memory cell involves injecting or extracting electric charges by Fowler-Nordheim effect into or from the floating gate. The floating-gate transistor has a first threshold voltage in the programmed state and a second threshold voltage in the erased state, greater than the threshold voltage in the programmed state. When a read voltage between the threshold voltages in the programmed and erased state is applied to the control gate of the floating-gate transistor, the latter remains OFF if it is in the erased state, which corresponds by convention to a logic “0”, and is ON if it is in the programmed state, which corresponds to a logic “1”. It will be understood that a reverse convention can be chosen. A write cycle of writing a data word in a hardware word of an EEPROM memory classically comprises a step of erasing all the memory cells of the hardware word to be written to and a step of selectively programming the memory cells according to the state of each bit of the data word to be written.
It is desirable to produce an EEPROM memory having a low erase-granularity for example the size of a hardware word, i.e., one or more bytes. It transpires that the smaller the granularity of an EEPROM or Flash memory, the higher the footprint and the cost of such a memory becomes.
Generally, Flash memories have an erase-granularity of the size of an entire sector of several pages, typically of 4 kilo-bytes. Some Flash memories are designed to emulate an EEPROM memory having an erase-granularity of the size of a word. For this purpose, a RAM memory is implemented to store the data of an entire sector. A datum is written by loading the sector containing the datum to be written into the RAM memory, by writing the new value of the datum in the RAM memory, by erasing the sector, and by transferring the updated sector of the RAM memory to the Flash memory. In addition to requiring additional management and RAM memory circuits that are relatively cumbersome, this method triggers cycles of erasing and programming not only the memory cells of the datum to be updated, but also of all the other memory cells of the accessed sector. Given that a memory cell can only withstand a limited number of such cycles, typically a hundred thousand cycles, the effect of this method is to considerably reduce the service life of such a memory. Such a mechanism has also been adapted to page-erasable EEPROM memories corresponding to a line of memory cells of the memory. Adapted to EEPROM memories, this mechanism enables a few memory cells of a page to be erased, for example a single word. This adaptation also contributes to reducing the duration of use of such a memory and to increasing the footprint of the latter.
It is also desirable to be able to further miniaturize the memory cells of an EEPROM memory, and to reduce the footprint of the circuits managing the memory. For this purpose, the size of the transistors can be decreased, which involves reducing some control voltages of the memory array, resulting in risks of partially programming or erasing certain memory cells.